The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.
Planarization processes such as chemical mechanical polishing (CMP) processes are performed as a part of semiconductor fabrication. For example, a CMP process may apply a slurry to a surface of a wafer that needs to be planarized. The slurry has corrosive properties and chemically etches the wafer. In conjunction with the application of the slurry, a polishing pad having a smooth surface is pressed against the surface of the wafer to grind the wafer surface. As a result, the wafer surface becomes substantially flattened (or planarized) to facilitate subsequent fabrication. Existing CMP methods have utilized various process control methods to ensure that the CMP process achieves the desired result. However, conventional CMP process control methods have not analyzed byproduct components generated during a CMP process, or use the byproduct component analysis for purposes of CMP process control.
Therefore, although existing methods and systems of performing planarization processes such as CMP have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.